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Verification Methodology Manual for SystemVerilog

Verification Methodology Manual for SystemVerilog 0.0分

资源最后更新于 2020-11-21 03:06:26

作者:Janick Bergeron

出版社:Springer

出版日期:2005-01

ISBN:9780387255385

文件格式: pdf

标签: Verification SystemVerilog VMM 电子 逻辑综合 编程 tech-software soc

简介· · · · · ·

Functional verification remains one of the single biggest challenges in the development of complex system-on-chip (SoC) devices. Despite the introduction of successive new technologies, the gap between design capability and verification confidence continues to widen. The biggest problem is that these diverse new technologies have led to a proliferation of verification point too...

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